题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
reg a_delay;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		a_delay<=0;
	end
	else begin
		a_delay<=a;
	end
end	
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		down<=0;
		rise<=0;
	end
	else begin
		if(!a & a_delay)begin
			down<=1;
			rise<=0;
		end
		else if(a & !a_delay)begin
			down<=0;
			rise<=1;
		end
		else begin
			down<=0;
			rise<=0;
		end
	end
end
endmodule