题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16
(
	input 				clk     ,
	input 				rst_n   ,
	input				valid_in,
	input	   [7:0]	data_in ,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg     bit_cnt;
reg     [7:0]   data_reg;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        bit_cnt <=  1'b0;
    else    if(valid_in)
        bit_cnt <=  bit_cnt + 1'b1;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_reg    <=  8'd0;
    else    if(valid_in && bit_cnt==1'b0)
        data_reg    <=  data_in;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        valid_out   <=  1'b0;
    else    if(bit_cnt == 1'b1 && valid_in)
        valid_out   <=  1'b1;
    else
        valid_out   <=  1'b0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_out    <=  15'd0;
    else    if(valid_in && bit_cnt==1'b1)
        data_out    <={data_reg,data_in};

endmodule