题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

reg [1:0]   cnt;
reg [7:0]   d_reg;  //存储输入的d值

always@(posedge clk or negedge rst)
    if(!rst)
        cnt <=  2'd0;
    else    
        cnt <=  cnt + 1'b1;


always@(posedge clk or negedge rst)
    if(!rst)
        input_grant <=  1'b0;
    else    if(cnt==2'd0)
        input_grant <=  1'b1;
    else
        input_grant <=  1'b0;

always@(posedge clk or negedge rst)
    if(!rst)
        d_reg   <= 8'd0;
    else    if(cnt==2'd0)
        d_reg   <=  d;
    else    
        d_reg   <=  d_reg;


always@(posedge clk or negedge rst)
    if(!rst)
        out <=  10'd0;
    else    if(cnt==2'd0)
        out <=  d;
    else    if(cnt==2'd1)
        out <=  (d_reg<<1) + d_reg;
    else    if(cnt==2'd2)
        out <=  (d_reg<<2) + (d_reg<<1) + d_reg;
    else    if(cnt==2'd3)
        out <=  d_reg<<3;


//*************code***********//
endmodule