`timescale 1ns/1ns module multi_pipe#( parameter size = 4 )( input clk , input rst_n , input [size-1:0] mul_a , input [size-1:0] mul_b , output reg [size*2-1:0] mul_out ); reg [size*2-1:0] temp [0:size-1]; integer i; always@(posedge clk or negedge rst_n) if(!rst_n) begin for(i=0;i<size;i=i+1) temp[i]<=0; end else begin for(i=0;i<size;i=i+1) temp[i] <= mul_b[i]? (mul_a <<i):0; end always@(posedge clk or negedge rst_n) if(!rst_n) mul_out <= 0; else mul_out <= temp[0] + temp[1] + temp[2] + temp[3] ; endmodule