题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//

reg [1:0] cur_state,next_state;
parameter s1=0;parameter s2=1;parameter s3=2;parameter s4=3;

always@(posedge clk or negedge rst)
begin
	if(!rst)
		cur_state<=s1;
	else
		cur_state<=next_state;
end

always@(*)
begin
	if(!rst)
		next_state=s1;
	else 
		case(cur_state)
			s1:next_state=s2;
			s2:next_state=s3;
			s3:next_state=s4;
			s4:next_state=s1;
			default:next_state=s1;
		endcase
end

always@(posedge clk or negedge rst)
begin
	if(!rst)
		clk_out<=0;
	else if(cur_state==s1)
		clk_out<=1;
	else
		clk_out<=0;
end

//*************code***********//
endmodule