题解 | #脉冲同步器（快到慢）#

解题思路：

①先将高频脉冲展宽，从sig_a脉冲来就开始展，展宽结束是低频时钟域收到信号再打两拍反馈回来，表示已经收到了无需再拉长；

②低频时钟域对拉长的信号打两拍，防止亚稳态；

③低频再打一拍，相当于有一个延迟，根据这个延迟一拍用组合逻辑生成了sig_b;

④用高频把sig_b打两拍反馈给高频，示意展宽结束。

参考代码如下：

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);
    reg sig_a_300;
    reg sig_a_300_r1, sig_a_300_r2;
    reg sig_b_r1;
    reg sig_b_300_r1, sig_b_300;
    
    always@(posedge clka or negedge rst_n)
        if(!rst_n)
            sig_a_300 <= 1'b0;
        else if(sig_a)
            sig_a_300 <= 1'b1;
        else if(sig_b_300)
            sig_a_300 <= 1'b0;
        else
            sig_a_300 <= sig_a_300;
    
    always@(posedge clkb or negedge rst_n)
        if(!rst_n) begin
            sig_a_300_r1 <= 1'b0;
            sig_a_300_r2 <= 1'b0;
        end
        else begin
            sig_a_300_r1 <= sig_a_300;
            sig_a_300_r2 <= sig_a_300_r1;
        end
    
    always@(posedge clkb or negedge rst_n)
        if(!rst_n)
            sig_b_r1 <= 1'b0;
        else
            sig_b_r1 <= sig_a_300_r2;
    
    assign sig_b = sig_a_300_r2 && ~sig_b_r1;
    
    always@(posedge clka or negedge rst_n)
        if(!rst_n) begin
            sig_b_300_r1 <= 1'b0;
            sig_b_300    <= 1'b0;
        end
    else begin
        sig_b_300_r1 <= sig_b;
        sig_b_300    <= sig_b_300_r1;
    end
            
endmodule