`timescale 1ns/1ns

module dajiang13(
    input  [7:0]    A,
    output [15:0]   B
	);

//*************code***********//

wire[15:0]C;
assign C=A;
assign B=(C<<7)+(C<<6)+(C<<5)+(C<<4)+(C<<3)+(C<<1)+C;//注意符号运算级
//*************code***********//

endmodule