题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter money_0=5;
parameter money_1=10;
parameter money_2=20;
reg d1_reg,d2_reg,d3_reg;
always@(posedge clk or negedge rst)begin 
	if(!rst)
	  begin 
		d1_reg<=0;
        d2_reg<=0;
		d3_reg<=0;
	  end
	  else 
	  begin d1_reg<=d1;
	  d2_reg<=d2;
	  d3_reg<=d3; end 
end
reg [2:0]cnt1,cnt2,cnt3;
always@(posedge clk or negedge rst)begin 
	if(!rst)
	  begin 
		cnt1<=0;
        cnt2<=0;
		cnt3<=0;
	  end
	  else if(flag)
		begin cnt1<=0;
        cnt2<=0;
		cnt3<=0; end 
	else if(d1) cnt1<=cnt1+1;
	else if(d2)cnt2<=cnt2+1;
	else if(d3) cnt3<=cnt3+1;
	else begin 
		cnt1<=cnt1;
        cnt2<=cnt2;
		cnt3<=cnt3; end 
end
wire flag;
assign flag=((cnt1*money_0+cnt2*money_1+cnt3*money_2)>=15)? 1:0;
always@(posedge clk or negedge rst)begin 
	if(!rst)
	begin out1<=0;
	     out2<=0;
	end
	else if(flag)
	begin out1<=1;
	     out2<=((cnt1*money_0+cnt2*money_1+cnt3*money_2)-15)/money_0;
	end
	else 	begin out1<=0;
	     out2<=0;
	end
end 
//*************code***********//
endmodule