`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); wire [7:0]result1; compare c1( // .clk(clk), // .rst_n(rst_n), .a(a), .b(b), .r(result1) ); wire [7:0]result2; compare c2( // .clk(clk), // .rst_n(rst_n), .a(result1), .b(c), .r(result2) ); // wire [7:0]result3; // compare c3( // .clk(clk), // .rst_n(rst_n), // .a(result1), // .b(result2), // .r(result3) // ); // assign d=result3; reg [7:0]d_reg; reg [7:0]d_reg2; always@(posedge clk or negedge rst_n)begin if(!rst_n)begin d_reg<=0; d_reg2<=0; end else begin d_reg<=result2; d_reg2<=d_reg; end end assign d=d_reg2; endmodule ////////////子模块比较器,使用组合逻辑电路/////////// module compare( // input clk, // input rst_n, input [7:0]a, input [7:0]b, output [7:0]r ); // reg [7:0]d_reg; //习惯了先将结果做一个寄存器 // always@(posedge clk or negedge rst_n)begin // if(!rst_n)begin // d_reg<=0; // end // else begin // //d_reg<=(a>b)?b:a; // if(b>a)begin d_reg<=a; end // else begin d_reg<=b; end // end // end // assign r=d_reg; assign r=(a>b)?b:a; endmodule
`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); wire [7:0]result1; compare c1( .clk(clk), .rst_n(rst_n), .a(a), .b(b), .r(result1) ); wire [7:0]result2; compare c2( .clk(clk), .rst_n(rst_n), .a(a), .b(c), .r(result2) ); wire [7:0]result3; compare c3( .clk(clk), .rst_n(rst_n), .a(result1), .b(result2), .r(result3) ); assign d=result3; endmodule ////////////子模块比较器/////////// module compare( input clk, input rst_n, input [7:0]a, input [7:0]b, output [7:0]r ); reg [7:0]d_reg; //习惯了先将结果做一个寄存器 always@(posedge clk or negedge rst_n)begin if(!rst_n)begin d_reg<=0; end else begin //d_reg<=(a>b)?b:a; if(b>a)begin d_reg<=a; end else begin d_reg<=b; end end end assign r=d_reg; endmodule
1.注意子模块的设计规范
2.子模块设计时接口大小要与调用接口大小一致