题解 | #同步FIFO#

`timescale 1ns/1ns

/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
                       parameter WIDTH = 8)(
     input wclk
    ,input wenc
    ,input [$clog2(DEPTH)-1:0] waddr  
    ,input [WIDTH-1:0] wdata          
    ,input rclk
    ,input renc
    ,input [$clog2(DEPTH)-1:0] raddr  
    ,output reg [WIDTH-1:0] rdata         
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
    if(wenc)
        RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
    if(renc)
        rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
    parameter    WIDTH = 8,
    parameter     DEPTH = 16
)(
    input                     clk        , 
    input                     rst_n    ,
    input                     winc    ,
    input                      rinc    ,
    input         [WIDTH-1:0]    wdata    ,

    output reg                wfull    ,
    output reg                rempty    ,
    output wire [WIDTH-1:0]    rdata
);
    wire                    wenc;
    reg [$clog2(DEPTH) : 0] waddr;
    reg [$clog2(DEPTH) : 0] raddr;
 
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wfull <= 'd0;
            rempty <= 'd0;
        end
        else begin
            wfull <= waddr == raddr + DEPTH;
            rempty <= waddr == raddr;
        end
    end
     
    assign wenc = winc && !wfull;
    assign renc = rinc && !rempty;
 
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            waddr <= 'd0;
        else if (wenc)
            waddr <= waddr + 'd1;
    end
     
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            raddr <= 'd0;
        else if (renc)
            raddr <= raddr + 'd1;
end

    dual_port_RAM #(.DEPTH (DEPTH),
                    .WIDTH (WIDTH))
    dual_port_RAM (
        .wclk  (clk  ),
        .wenc  (wenc ),
        .waddr (waddr),
        .wdata (wdata),
        .rclk  (clk  ),
        .renc  (renc ),
        .raddr (raddr),
        .rdata (rdata)
    );
    

    
endmodule