题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
wire [4:0] c;
assign c[0] = C_1;

genvar i;
generate for(i=0;i<4;i=i+1)
begin: add
assign S[i] = A_in[i] ^ B_in[i] ^c[i];
assign c[i+1] = (A_in[i] && B_in[i]) || ((A_in[i] ^ B_in[i]) && c[i]);   
end
endgenerate

assign CO = c[4];


endmodule