`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)
    cnt<=0;
    else if(cnt==7)
    cnt<=0;
    else 
    cnt<=cnt+1;
end
always@(posedge clk or negedge rst_n)begin 
    if(!rst_n)
     Q<=0;
     else if(cnt<=3)
     Q<={1'b1,Q[3:1]};
     else 
     Q<={1'b0,Q[3:1]};
end
endmodule