题解 | #时钟切换#

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output wire clk_out
);
//*************code***********//
reg out0;
reg out1;
always@(negedge clk0 or negedge rst)
begin if(!rst)
    out0<=0;
	else out0<=~sel&~out1;
end
always@(negedge clk1 or negedge rst)
begin if(!rst)
    out1<=0;
	else out1<=sel&(~out0);
end
assign clk_out=(clk0&out0)|(out1&clk1);
//*************code***********//
endmodule