题解 | #任意奇数倍时钟分频#

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
    reg [$clog2(dividor):0] cnt1;
    reg clk1, clk2;
    
    //计数模块，计数到dividor-1归0，因为整个电路并行执行，复位后cnt为0，
    //第一个时钟上升沿到来时，cnt为0，整个电路同时工作；所以cnt为0时整个电路已经一起工作过一次。
    always @ (posedge clk_in, negedge rst_n) begin
        if(!rst_n) begin
            cnt1 <= 0;
        end
        else
            cnt1 <= (cnt1 == dividor-1 ) ? 0 : cnt1 + 1;
    end
    
    //上升沿有效，在(dividor - 1)>>1和(dividor-1)时翻转
    always @ (posedge clk_in, negedge rst_n)begin
        if(!rst_n) begin
            clk1 <= 1'b0;
        end
        else if(cnt1 == (dividor - 1)>>1) begin
            clk1 <= ~clk1;
        end
        else if (cnt1 == (dividor-1)) begin
            clk1 <= ~clk1;
        end
        else begin
            clk1 <= clk1;
        end        
                     
    end
    //下升沿有效，在(dividor - 1)>>1和(dividor-1)时翻转
    always @ (negedge clk_in, negedge rst_n)begin
        if(!rst_n) begin
            clk2 <= 1'b0;
        end
        else if(cnt1 == (dividor - 1)>>1) begin
            clk2 <= ~clk2;
        end
        else if (cnt1 == (dividor-1)) begin
            clk2 <= ~clk2;
        end
        else begin
            clk2 <= clk2;
        end
              
    end
    assign clk_out = clk1 || clk2;
    
endmodule