题解 | #使用generate…for语句简化代码#

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);

    genvar i ;
    generate
        for(i = 0 ; i <= 7 ; i = i + 1)
        begin:for_loop //名字一定要有
            assign data_out[i] = data_in[7-i];
        end
    endgenerate

 
endmodule


`timescale 1ns/1ns
module testbench();
	reg [7:0] data_in;
	wire [7:0] data_out;
	
initial begin
	$dumpfile("out.vcd");
	$dumpvars(0,testbench);

end 


initial begin
	data_in <= 8'd1;
	#10
	data_in <= 8'd10;
end
gen_for_module dut(
	.data_in(data_in),
	.data_out(data_out)
);

endmodule