题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire       Y   
);
reg[1:0]state;
reg[1:0]next_state;
wire [2:0]sel;
assign sel={state,A};
always @(posedge clk or posedge rst_n)
begin if(rst_n==0)
state<=0;
else 
 state<=next_state;
end
 always @(*)
   begin 
    case (sel)
   3'b000: begin next_state=2'b01; end
   3'b010: begin next_state= 2'b10; end
   3'b100: begin next_state= 2'b11; end
   3'b110: begin next_state= 2'b00; end
   3'b001: begin next_state= 2'b11; end
   3'b011: begin next_state= 2'b00; end
   3'b101: begin next_state= 2'b01; end
   3'b111: begin next_state= 2'b10;end
    default:next_state<=00;
    endcase
 end

assign Y=(state===2'b11)?1:0;
endmodule