题解 | #输入序列不连续的序列检测#(最规范的段式状态机)

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
  
  reg [4:0] cur_state;
  reg [4:0] nex_state;
  
  parameter IDLE = 5'b00_001,
            S0   = 5'b00_010,
			S1   = 5'b00_100,
            S2   = 5'b01_000,
			S3   = 5'b10_000;
  
  always@(posedge clk or negedge rst_n)begin
      if(!rst_n)
          cur_state <= IDLE           ;
      else
          cur_state <= nex_state      ;	  
  end
  
  always@(*)begin
     case(cur_state)
	    IDLE:begin 
		    if(data_valid == 1'b1)begin
			    if(data == 1'b0)
				    nex_state = S0    ;
				else
				    nex_state = IDLE  ;    
			end
			else begin
			    nex_state = IDLE;
			end
		end	
		S0:begin //data 序列：0
		    if(data_valid == 1'b1)begin
			    if(data == 1'b1)
				    nex_state = S1    ;
				else
				    nex_state = S0    ;    
			end
			else begin
			    nex_state = S0;
			end
		end	
		S1:begin //data 序列：01
		    if(data_valid == 1'b1)begin
			    if(data == 1'b1)
				    nex_state = S2    ;
				else 
				    nex_state = S0    ;    
			end
			else begin
			    nex_state = S1;
			end
		end	
		S2:begin //data 序列：011
		    if(data_valid == 1'b1)begin
			    if(data == 1'b0)
				    nex_state = S3    ;
				else
				    nex_state = IDLE  ;    
			end
			else begin
			    nex_state = S1        ;
			end
		end	
		S3:begin //data 序列：0110
		    if(data_valid == 1'b1)begin
			    if(data == 1'b0)
				    nex_state = S0    ;
				else
				    nex_state = IDLE  ;    
			end
			else begin
			    nex_state = IDLE      ;
			end
		end	
		default: nex_state = IDLE     ;
	 endcase
  end
  
  always@(posedge clk or negedge rst_n)begin
      if(!rst_n)
	      match <= 1'b0;
	  else begin
	      case(nex_state)
		      S3     : match <= 1'b1 ;
			  default: match <= 1'b0 ;
		  endcase
	  end
  end
endmodule