`timescale 1ns/1ns

module dajiang13(
    input  [7:0]    A,
    output [15:0]   B
	);

//*************code***********//
    assign B = (A<<7) + (A<<6) + (A<<5) + (A<<4) + (A<<3) + (A<<1) + A;

//*************code***********//

endmodule