题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns
 
module width_24to128(
    input               clk         ,  
    input               rst_n       ,
    input               valid_in    ,
    input   [23:0]      data_in     ,
 
    output  reg         valid_out   ,
    output  reg [127:0] data_out
);
 
reg [3:0]  cnt;
reg [127:0] reg_data;
 
 
always@(posedge clk or negedge rst_n) begin
    if(~rst_n)
        cnt <= 0;
    else
        cnt <= valid_in ? cnt + 3 : cnt;
end
 
 
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        reg_data <= 0;
    end
    else begin
        if (valid_in) begin
            reg_data <= {reg_data, data_in};
        end
    end
end
 
always@(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        valid_out <= 0;
        data_out  <= 0;
    end
    else if (valid_in && cnt >= 13 ) begin
        valid_out <= 1;
        case(16-cnt)
            1 : data_out  <= {reg_data,data_in[23:16]};
            2 : data_out  <= {reg_data,data_in[23:8]};
            3 : data_out  <= {reg_data,data_in};
        endcase
    end
    else begin
        valid_out <= 0;
    end
end
 
endmodule