题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
wire [3:0]gray;
assign gray=data_in^(data_in>>1);
reg [3:0]gray_d1;
reg [3:0]gray_d2;
always@(posedge clk_b or negedge brstn)
begin if(!brstn)
     begin 
		gray_d1<=0;
		gray_d2<=0;
	 end
	 else if(data_en)
	  begin 
		gray_d1<=gray;
		gray_d2<=gray_d1;
	 end
end
wire [3:0] gray_bin;
assign gray_bin={gray_d2[3],gray_d2[2]^gray_bin[3],gray_d2[1]^gray_bin[2],gray_d2[0]^gray_bin[1]};
always@(posedge clk_b or negedge brstn)
begin if(!brstn)
     dataout<=0;
	 else 
	 dataout<=gray_bin;
end
endmodule