小小凡是一艘船

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题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); wire [7:0] out_1; wir...

2023-10-03

0 315

题解 | #位拆分与运算#

`timescale 1ns/1ns module data_cal( input clk, input rst, input [15:0]d, input [1:0]sel, output [4:0]out, output validout ); //*************code****...

2023-10-03

0 288

题解 | #256选1选择器#

`timescale 1ns/1ns module top_module ( input [255:0] in, input [7:0] sel, output out ); // reg out_temp; // genvar i; // generate // for(i=0...

2023-10-03

0 243

题解 | #对信号按位操作#

`timescale 1ns/1ns module top_module( input [4:0] in, output out_and, output out_or, output out_xor ); assign out_and = ∈ as...

2023-10-03

0 221

题解 | #信号反转输出#

`timescale 1ns/1ns module top_module( input [15:0] in, output [15:0] out ); reg [15:0] out_reg; // assign out = {in[0],in[1],in[2],in[3...

2023-10-03

0 264

题解 | #信号顺序调整#

`timescale 1ns/1ns module top_module( input [15:0] in, input clk, input rst_n, output reg [15:0] out ); reg [2:0] cnt; reg [...

2023-10-02

0 230

题解 | #多位信号#

`timescale 1ns/1ns module top_module( input [2:0] in, output reg a, output reg b, output reg c ); always@(*) begin ...

2023-10-02

1 275

题解 | #数据串转并电路#

`timescale 1ns/1ns module s_to_p( input clk , input rst_n , input valid_a , input data_a , output reg ready_a , o...

2023-09-28

0 288

题解 | #脉冲同步电路#

`timescale 1ns/1ns module pulse_detect( input clk_fast , input clk_slow , input rst_n , input data_in , output dataou...

2023-09-26

1 351

题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps module pulse_detect( input clka , input clkb , input rst_n , input sig_a , output sig_b ); re...

2023-09-07

0 335