题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0] u,v;

test u1(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(b),
	.d(u)
);

test u2(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(c),
	.d(v)
);

test u3(
	.clk(clk),
	.rst_n(rst_n),
	.a(u),
	.b(v),
	.d(d)
);
endmodule

module test(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output [7:0]d
);
reg [7:0] d;
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			d <= 8'd0;
		else if(a>b)
			d<= b;
		else 
			d <= a;
	end
	
endmodule