题解 | #任意奇数倍时钟分频#

能通过仿真

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
    reg [$clog2(dividor):0] cnt_r;
    reg clk_pos;
    reg clk_neg;
    
    always @(negedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            cnt_r <= 'd0;
        end
        else begin
            cnt_r <= cnt_r == dividor - 'd1 ? 'd0 : cnt_r + 'd1;
        end
    end
    
    always @(posedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            clk_pos <= 'd0;
        end
        else if (cnt_r == (dividor >> 1) - 1) begin
            clk_pos <= 'd1;
        end
        else if (cnt_r == dividor - 'd1) begin
            clk_pos <= 'd0;
        end
    end
    
    
    always @(negedge clk_in or negedge rst_n) begin
        if (!rst_n) begin
            clk_neg <= 'd0;
        end
        else if (cnt_r == (dividor >> 1) - 1) begin
            clk_neg <= 'd1;
        end
        else if (cnt_r == dividor - 'd1) begin
            clk_neg <= 'd0;
        end
    end
    
    assign clk_out = clk_pos & clk_neg;
endmodule