题解 | #序列检测器（Moore型）#

`timescale 1ns/1ns

module det_moore(
   input                clk   ,
   input                rst_n ,
   input                din   ,
 
   output	reg         Y   
);
    parameter S0 = 3'd0;
    parameter S1 = 3'd1;
    parameter S2 = 3'd2;
    parameter S3 = 3'd3;
    parameter S4 = 3'd4;
    reg [3:0] cstate, nstate;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cstate <= S0;
        end
        else begin
            cstate <= nstate;
        end
    end
    always@(*) begin
        case(cstate)
            S0: begin
                nstate = din?S1:S0;
            end
            S1: begin
                nstate = din?S2:S0;
            end
            S2: begin
                nstate = din?S2:S3;
            end
            S3: begin
                nstate = din?S4:S0;
            end
            S4: begin
                nstate = din?S1:S0;
            end
        endcase
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            Y <= 1'b0;
        end
        else begin
            Y <= (cstate==S4);
        end
    end
endmodule