题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
    parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
    reg [2:0] c_state;
    reg [2:0] n_state;
    
    always@(posedge clk or negedge rst) begin: part1
        if(~rst)
            c_state <= S0;
        else
            c_state <= n_state;
    end
    
    always@(*) begin
        case(c_state)
            S0: begin
                n_state = data ? S1:S0;
                flag = 0;
            end
            S1: begin
                n_state = data ? S2:S1;
                flag = 0;
            end
            S2: begin
                n_state = data ? S3:S2;
                flag = 0;
            end
            S3: begin
                n_state = data ? S4:S3;
                flag = 0;
            end
            S4: begin
                n_state = data ? S1:S0;
                flag = 1;
            end
            default: begin
                n_state = S0;
                flag = 0;
            end
        endcase
    end

//*************code***********//
endmodule