`timescale 1ns/1ns

module fsm2(
    input wire clk  ,
    input wire rst  ,
    input wire data ,
    output reg flag
);
//*************code***********//
    parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100;
    reg [2:0] sta,nsta;
    always@(posedge clk or negedge rst)
    if(!rst)
        sta <= S0;
    else
        sta <= nsta;
   
    always@(*)begin
    flag = 0;//初始化 就不用写那么多else了
    case(sta)
    S0:nsta = data?S1:S0;
    S1:nsta = data?S2:S1;
    S2:nsta = data?S3:S2;
    S3:nsta = data?S4:S3;
    S4:begin
    nsta = data?S1:S0;
    flag = 1;
    end
    default:nsta = S0;
    endcase
    end

//*************code***********//
endmodule