alt

题目说了只有sel = 0时的输入才有效,因此需要进行锁存,这点需要注意。

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//
    reg [15:0] d_tmp;
    
    always@(posedge clk or negedge rst) begin
        if(~rst) begin
            validout <= 0;
            out <= 5'b0;
            d_tmp <= 16'b0;
        end
        else begin
            case(sel)
                0: begin
                    validout <= 0;
                    out <= 5'b0;
                    d_tmp <= d;
                end
                1: begin
                    validout <= 1;
                    out <= d_tmp[3:0] + d_tmp[7:4];
                end
                2: begin
                    validout <= 1;
                    out <= d_tmp[3:0] + d_tmp[11:8];
                end
                3: begin
                    validout <= 1;
                    out <= d_tmp[3:0] + d_tmp[15:12];
                end
                default: begin
                    validout <= 0;
                    out <= 5'b0;
                end
            endcase
        end
    end
    
//*************code***********//
endmodule