题解 | #根据状态转移表实现时序电路#

结合前辈的写法，写的三段式状态机，第三段采用时序always

reg [1:0] curr_state;
reg [1:0] next_state;
// one step
always @ (posedge clk or negedge rst_n)
    begin
        if( ~rst_n ) begin
            curr_state <= 2'b00;
            next_state <= 2'b00;
        end 
        else begin
            curr_state <= next_state;
        end 
    end 
 
// two step
always @ (*)
    begin
        case(curr_state)
            2'b00 : next_state = (A == 1'b1) ? 2'b11 : 2'b01;
            2'b01 : next_state = (A == 1'b1) ? 2'b00 : 2'b10;
            2'b10 : next_state = (A == 1'b1) ? 2'b01 : 2'b11;
            2'b11 : next_state = (A == 1'b1) ? 2'b10 : 2'b00;
            default : next_state = 2'b00;
        endcase
    end
//three
reg out_buffer;
always @ (posedge clk or negedge rst_n)
    begin
        if( ~rst_n ) begin
            out_buffer<=0;
        end 
        else if(A==0) begin
            out_buffer<=(curr_state=='b10)?1:0;
            //out_buffer<=(next_state=='b11)?1:0;  //修改V2.0，这个条件也可以，感觉更好理解
        end
        else begin
            out_buffer<=(curr_state=='b00)?1:0;
            //out_buffer<=(next_state=='b11)?1:0;   //V2.0
        end
    end
assign Y=out_buffer;