题解 | #自动贩售机2#

简化版代码如下，仿真正确。

`timescale 1ns/1ns

module seller2(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire sel ,
	
	output reg out1,
	output reg out2,
	output reg out3
);
//*************code***********//
    localparam IDLE = 3'd0, // 0
               S0   = 3'd1, // 0.5
               S1   = 3'd2, // 1
               S2   = 3'd3, // 1.5
               S3   = 3'd4, // 2
               S4   = 3'd5, // 2.5
               S5   = 3'd6; // 3
    reg [2:0] nxt_state_w;
    reg [2:0] cur_state_r;

//*************code***********//
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            cur_state_r <= 'd0;
        end
        else begin
            cur_state_r <= nxt_state_w;
        end
    end
        
    always @(*) begin
        case(cur_state_r)
            IDLE: begin
                case({d1, d2})
                    2'b10: nxt_state_w = S0;
                    2'b01: nxt_state_w = S1;
                    default: nxt_state_w = nxt_state_w;
                endcase
            end
            S0: begin
                case({d1, d2})
                    2'b10: nxt_state_w = S1;
                    2'b01: nxt_state_w = S2;
                    default: nxt_state_w = nxt_state_w;
                endcase
            end
            S1: begin
                case({d1, d2})
                    2'b10: nxt_state_w = S2;
                    2'b01: nxt_state_w = S3;
                    default: nxt_state_w = nxt_state_w;
                endcase
            end
            S2: begin
                if (sel==1'b0)
                    nxt_state_w = IDLE;
                else begin
                    case({d1, d2})
                        2'b10: nxt_state_w = S3;
                        2'b01: nxt_state_w = S4;
                        default: nxt_state_w = nxt_state_w;
                    endcase
                end
            end
            S3: begin
                if (sel==1'b0)
                    nxt_state_w = IDLE;
                else begin
                    case({d1, d2})
                        2'b10: nxt_state_w = S4;
                        2'b01: nxt_state_w = S5;
                        default: nxt_state_w = nxt_state_w;
                    endcase
                end
            end
            default: nxt_state_w = IDLE;
        endcase
    end
        
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            out1 <= 'd0;
            out2 <= 'd0;
            out3 <= 'd0;
        end
        else begin
            out1 <= !sel && nxt_state_w >= S2;
            out2 <=  sel && nxt_state_w >= S4;
            out3 <= (!sel && nxt_state_w == S3) ||
                    ( sel && nxt_state_w == S5)  ;
        end
    end
    
endmodule