题解 | #脉冲同步电路#

module pulse_detect(
    input                 clk_fast    , 
    input                 clk_slow    ,   
    input                 rst_n        ,
    input                data_in        ,

    output               dataout
);
    reg sync_f;
    always@(posedge clk_fast or negedge rst_n)
    if(!rst_n)
        sync_f <= 0;
    else 
        sync_f <= data_in?~sync_f:sync_f;
    
    reg sync1_s,sync2_s,sync3_s;
    always @(posedge clk_slow or negedge rst_n)
    if(!rst_n)
        {sync1_s,sync2_s,sync3_s}<=0;
    else
        {sync1_s,sync2_s,sync3_s}<={sync_f,sync1_s,sync2_s}; 

    assign dataout = sync2_s^sync3_s;       

endmodule