题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4;
reg [2:0] current_state,next_state;

always @(*)
begin
	if(data_valid)
	begin
    case (current_state)
	s0: next_state = data ? s0 : s1;
	s1: next_state = data ? s2 : s1;
	s2: next_state = data ? s3 : s1;
	s3: next_state = data ? s0 : s4;
	s4: next_state = data ? s2: s1;
	default:next_state =s0;
	endcase
	end
	else
	begin
    next_state =s0;
	end
end

			always @ (posedge clk or negedge rst_n)
			begin
			if(!rst_n)
			begin
			current_state<=s0;
			end
			else 
			begin
			current_state<=next_state;
			end
			end


	always@(*)
	begin
	if(!rst_n)
	begin
	match=1'b0;
	end
		else
		begin
	  match=(current_state==s4);
		end
	end


endmodule