看了其他的题解发现没人用全等号(===)来做的,我来写一个题解,答案如下:

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
    reg q;
    always@(posedge clk or negedge rst_n)begin 
        if(!rst_n) begin rise <= 0; down <= 0; q<=0;end
        else  q<=a;
        rise <=  ((a & ~q)===1)?1:0;  
        down <=  ((~a & q)===1)?1:0;  
    end
  endmodule