module calculation(
	input clk,
	input rst_n,
	input [3:0] a,
	input [3:0] b,
	output [8:0] c
	);
wire [7:0]temp_out0,temp_out1;
mul_4 u0(clk,rst_n,a,4'd12,temp_out0);
mul_4 u1(clk,rst_n,b,4'd5,temp_out1);	
assign c=temp_out0+temp_out1;
endmodule	
module 	mul_4(
input clk ,rst_n,
input [3:0] a,b,
output reg  [7:0] out
);
reg [6:0]temp0,temp1,temp2,temp3;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
temp0<=0;
temp1<=0;
temp2<=0;
temp3<=0;
out<=0;
end
else
begin
 temp0<= b[0] ? {3'b0,a}  :0;
 temp1<= b[1] ? {2'b0,a,1'b0} :0;
 temp2<= b[2] ? {1'b0,a,2'b0} :0;
 temp3<= b[3] ? {a,3'b0}  :0;
 out<=temp0+temp1+temp2+temp3;	
end
end

endmodule

`timescale 1ns/1ns
module textbench();
reg clk,rst_n;
reg[3:0] a,b;
wire[8:0]c;
calculation u0 (
	clk,
	rst_n,
	a,
    b,
	c
	);

always #5clk=~clk;

 initial begin
rst_n=0;clk=0;
a=0;b=0;
#6 rst_n=1;
#12 a=2;b=1;
#13 a=1;b=2;
#20
$finish;
end

endmodule

仿真结果如下: