`timescale 1ns/1ns module multi_pipe#( parameter size = 4 )( input clk , input rst_n , input [size-1:0] mul_a , input [size-1:0] mul_b , output reg [size*2-1:0] mul_out ); wire [2*size-1 : 0] a,b; reg [2*size-1 : 0]temp0,temp1,temp2,temp3; assign a=mul_a; assign b=mul_b; always @(posedge clk or negedge rst_n) begin if(!rst_n) begin temp0<=0; temp1<=0; temp2<=0; temp3<=0; end else begin temp0 <= b[0] ? a : 0; temp1<= b[1] ? a<<1 : 0; temp2<= b[2] ? a<<2 : 0; temp3<= b[3] ? a<<3 : 0; end end always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin mul_out=0; end else begin mul_out=temp0+temp1+temp2+temp3; end end endmodule