含有无关项的序列检测,相对于固定序列,判断时,按位判断即可满足组题意。

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg [8:0]	r_a;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		r_a <= 9'b1_1111_1111;
	end
	else begin
		r_a <= {r_a[7:0],a};
	end
end
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		match <= 1'b0;
	end
	else if ((r_a[8:6] == 3'b011) && (r_a[2:0] == 3'b110))begin
		match <= 1'b1;
	end
	else begin
		match <= 1'b0;
	end
end
endmodule