题解 | #RAM的简单实现#

实际的ram需要控制读写不能冲突，这道题目没有考虑这个情况。

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    reg [3:0] ram [7:0];
    integer i;
    always@(posedge clk or negedge rst_n) begin: write_ram
        if(~rst_n) begin
            for(i = 0 ; i < 8; i = i + 1)
                ram[i] <= 4'b0;
        end
        else if(write_en)
            ram[write_addr] <= write_data;
    end
    
    always@(posedge clk or negedge rst_n) begin: read_ram
        if(~rst_n)
            read_data <= 4'b0;
        else if(read_en)
            read_data <= ram[read_addr];
    end
    
endmodule