# 题解主体

 clkin clkout2 clkout4 clkout8 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 0 0 1

//2 分频

reg                  clk_div2 ;

always @(posedge clk_in or negedge rst) begin

if (!rst) begin

clk_div2     <= 'b0 ;

end

else begin

clk_div2     <= ~clk_div2 ;

end

end

assign       clk_out2 = clk_div2 ;

//4 分频

reg                  clk_div4 ;

always @(posedge clk_out2 or negedge rst) begin

if (!rst) begin

clk_div4     <= 'b0 ;

end

else begin

clk_div4     <= ~clk_div4 ;

end

end

assign clk_out4      = clk_div4 ;

//8 分频

reg                  clk_div8 ;

always @(posedge clk_out4 or negedge rst) begin

if (!rst) begin

clk_div8     <= 'b0 ;

end

else begin

clk_div8     <= ~clk_div8 ;

end

end

assign clk_out8      = clk_div8 ;

# 参考答案

````timescale 1ns/1ns

module even_div
(
input     wire rst ,
input     wire clk_in,
output    wire clk_out2,
output    wire clk_out4,
output    wire clk_out8
);

//2 分频
reg                  clk_div2 ;
always @(posedge clk_in or negedge rst) begin
if (!rst) begin
clk_div2     <= 'b0 ;
end
else begin
clk_div2     <= ~clk_div2 ;
end
end
assign       clk_out2 = clk_div2 ;

//4 分频
reg                  clk_div4 ;
always @(posedge clk_out2 or negedge rst) begin
if (!rst) begin
clk_div4     <= 'b0 ;
end
else begin
clk_div4     <= ~clk_div4 ;
end
end
assign clk_out4      = clk_div4 ;

//8 分频
reg                  clk_div8 ;
always @(posedge clk_out4 or negedge rst) begin
if (!rst) begin
clk_div8     <= 'b0 ;
end
else begin
clk_div8     <= ~clk_div8 ;
end
end
assign clk_out8      = clk_div8 ;

endmodule```