题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	reg a_tem;

always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		a_tem <= 1'b0;//这里不对a进行初始化因为如果在if对a赋值而在else不对a赋值会出现latch
		              //谁家好人会对输入信号初始化？无语了！！！
	else
		a_tem <= a;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		 rise <= 1'b0;
		 down <= 1'b0;
	end
	else if (!a_tem && a == 1) begin
		 rise <= 1'b1;
		 down <= 1'b0;
	end
	else if (a_tem & !a == 1) begin
		rise <= 1'b0;
		down <= 1'b1;
	end
	else begin
		rise <= 1'b0;
		down <= 1'b0;
	end
end	

endmodule