题解 | #异步复位同步释放#

`timescale 1ns/1ns

module ali16(
input clk,
input rst_n,
input d,
output reg dout
 );

//*************code***********//
    reg rst_n_sync_r1,rst_n_sync_r2;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            {rst_n_sync_r1,rst_n_sync_r2} <= 'd0;
        end
        else begin
            {rst_n_sync_r1,rst_n_sync_r2} <= {1'b1,rst_n_sync_r1};
        end
    end
    
    always@(posedge clk or negedge rst_n_sync_r2) begin
        if(!rst_n_sync_r2) begin
            dout <= 1'b0;
        end
        else begin
            dout <= d;
        end
    end

//*************code***********//
endmodule