题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,
	output reg [3:0]number,
	output reg zero
	);
    reg [3:0] out;
	always @(posedge clk or negedge rst_n)
	begin
	if(!rst_n)
	begin
	out<=4'd0;
	number<=4'd0;
	end
	else
	begin
	if(set)
	begin
	out<=set_num;
	end
	else
	begin
	out<= out==4'd15 ? 4'd0 : out +4'd1;
	end
	number<=out;
	end
	end
		always@(posedge clk or negedge rst_n)
		begin
			if(!rst_n)
			begin
				zero<=1'b0;
			end
			else
			begin
				zero<= out ==4'd0 ;

			end
		end

endmodule

`timescale 1ns/1ns
module testbench();
    reg rst,mode;
	reg clk=1;
	wire [3:0]number;
	reg[3:0] set_num;
	wire  zero;
	 count_module u1(
	. clk(clk),
	.set(mode),
	.set_num(set_num),
	.rst_n(rst),
    .number(number),
	.zero(zero)
);
	always #5 clk = ~clk;  // Create clock with period=10 
  initial begin
  rst=0;
  set_num=4'd0;
 #10 rst=1;mode=0;
 #200 mode=1;set_num=4'd10;
  #10 mode=0;
 #200 ;
 $finish;
end  
    
endmodule

仿真波形图如下：