题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
    parameter S0 = 'd0;
    parameter S1 = 'd1;
    parameter S2 = 'd2;
    parameter S3 = 'd3;
    reg [5:0] cnt;
    reg [1:0] cstate, nstate;
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cstate <= S0;
        end
        else begin
            cstate <= nstate;
        end
    end
    always@(*) begin
        case(cstate)
            S0: begin
                nstate = (cnt=='d9)?S1:S0;
            end
            S1: begin
                nstate = (cnt=='d4)?S2:S1;
            end
            S2: begin
                nstate = (cnt=='d59)?S0:S2;
            end
            default: begin
                nstate = S0;
            end
        endcase
    end
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cnt <= 'd0;
        end
        else begin
            if(pass_request & (cstate==S3) & (cnt>='d10)) begin
                cnt <= 'd10;
            end
            else begin
                if(cstate!=nstate) begin
                    cnt <= 'd0;
                end
                else begin
                    cnt <= cnt + 'd1;
                end
            end
        end
    end
    assign clock = (cstate==S0)?('d10-cnt):((cstate==S1)?('d5-cnt):('d60-cnt));
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            {red,yellow,green} <= 'd0;
        end
        else begin
            {red,yellow,green} <= {(cstate==S0),(cstate==S1),(cstate==S2)};
        end
    end
endmodule