题解主体

       首先确定second的取值逻辑：当minute=60时停止计数，即保持second为0；当second=60时，下一个周期second置为1。其余情况second 等于前一时刻的值加一。

       always @(posedge clk or negedge rst_n)

              if (!rst_n)

                     begin

                            second <= 6'd0;

                     end

              else if(second == 6'd60)

                     begin

                            second <= 6'd1;

                     end

              else if (minute == 60)

                     second <= second;            

              else

                     second <= second+1'd1;

       然后明确minute的取值逻辑：当second=60，minute等于前一时刻的值加一。其余情况，minute保持不变。

              always @(posedge clk or negedge rst_n)

              if (!rst_n)

                     begin

                            minute <= 6'd0;

                     end

              else if (second == 6'd60)

                     begin

                            minute <= minute+1;

                     end

              else

                     begin    

                            minute <= minute;

                     end

参考答案

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,

	output reg [5:0]second,
	output reg [5:0]minute
	);

	
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			begin 
				minute <= 6'd0;
			end
		else if (second == 6'd60)
			begin
				minute <= minute+1;
			end
		else 
			begin	
				minute <= minute;
			end
		
	always @(posedge clk or negedge rst_n)
		if (!rst_n)
			begin 
				second <= 6'd0;
			end
		else if(second == 6'd60)
			begin
				second <= 6'd1;
			end
		else if (minute == 60)
			second <= 0;		
		else
			second <= second+1'd1;
endmodule