题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

parameter s0='b0001,s1='b0010,s2='b0100,s3=1000;

reg [3:0] state,next_state;

//*************code***********//
always@(posedge clk or negedge rst) begin
  if(!rst) begin
	state <= s0;
  end
  else begin
	state <= next_state;
  end
end

always@(*) begin
  case(state)
    s0:next_state = s1;
	s1:next_state = s2;
	s2:next_state = s3;
	s3:next_state = s0;
    default:next_state = s0;
  endcase
end

always@(posedge clk or negedge rst) begin
  if(!rst) begin
	clk_out <= 'b0;
  end
  else if(state == s0) begin
	clk_out <= 'b1;
  end
  else begin
	clk_out <= 'b0;
  end
end

//*************code***********//
endmodule