`timescale 1ns/1ns
module clk_divider
#(parameter dividor = 5)
( input clk_in,
input rst_n,
output clk_out
);
parameter qq = dividor ;
reg [qq-1:0] cnt;
always @(posedge clk_in or negedge rst_n) begin
if(!rst_n)
cnt <= 'd0;
else if(cnt==qq-1)
cnt <= 'd0;
else
cnt <= cnt + 1'b1;
end
reg clk1,clk2;
always @(posedge clk_in or negedge rst_n) begin
if(!rst_n)
clk1<=1'b1;
else if(cnt==qq-1)
clk1<=~clk1;
else
clk1 <= clk1;
end
always @(negedge clk_in or negedge rst_n) begin
if(!rst_n)
clk2<=1'b1;
else if(cnt==(qq-1)/2)
clk2<=~clk2;
else
clk2 <= clk2;
end
assign clk_out = clk1 ^ clk2;
endmodule
module clk_divider
#(parameter dividor = 5)
( input clk_in,
input rst_n,
output clk_out
);
parameter qq = dividor ;
reg [qq-1:0] cnt;
always @(posedge clk_in or negedge rst_n) begin
if(!rst_n)
cnt <= 'd0;
else if(cnt==qq-1)
cnt <= 'd0;
else
cnt <= cnt + 1'b1;
end
reg clk1,clk2;
always @(posedge clk_in or negedge rst_n) begin
if(!rst_n)
clk1<=1'b1;
else if(cnt==qq-1)
clk1<=~clk1;
else
clk1 <= clk1;
end
always @(negedge clk_in or negedge rst_n) begin
if(!rst_n)
clk2<=1'b1;
else if(cnt==(qq-1)/2)
clk2<=~clk2;
else
clk2 <= clk2;
end
assign clk_out = clk1 ^ clk2;
endmodule