题解 | #整数倍数据位宽转换8to16#

和8to12很类似。

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    reg cnt;
    reg [7:0] data_in_r1;
    
    always@(posedge clk or negedge rst_n) begin: count_and_register_input
        if(~rst_n) begin
            cnt <= 0;
            data_in_r1 <= 8'b0;
        end
        else if(valid_in) begin
            cnt <= (cnt == 1) ? 0:cnt+1;
            data_in_r1 <= data_in;
        end
    end
    
    always@(posedge clk or negedge rst_n) begin: gen_output
        if(~rst_n) begin
            valid_out <= 0;
            data_out <= 16'b0;
        end
        else if(valid_in && cnt == 1) begin 
            valid_out <= 1;
            data_out <= {data_in_r1, data_in};
        end
        else
            valid_out <= 0;
    end
    
endmodule