alt

这是典型的采用多周期路径同步多比特信号的跨时钟域数据传输方式。

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
    reg data_en_r1;
    reg data_en_r2;
    always@(posedge clk_b or negedge brstn) begin: reg2
        if(~brstn) begin
            data_en_r1 <= 0;
            data_en_r2 <= 0;
        end
        else begin
            data_en_r1 <= data_en;
            data_en_r2 <= data_en_r1;
        end
    end
    
    always@(posedge clk_b or negedge brstn) begin: syn_data_to_clkb
        if(~brstn)
            dataout <= 4'b0;
        else if(data_en_r2)
            dataout <= data_in;
    end
            
endmodule