四个下降沿高电平 四个上升沿低电平 一个计数器记录电平变换,并控制计数器工作
`timescale 1ns/1ns
module odo_div_or ( input wire rst , input wire clk_in, output wire clk_out7 );
reg [2:0] count1 = 0;
reg [2:0] count2 = 0;
reg flag = 0;
reg waveout = 0;
assign clk_out7 = flag;
always@(posedge clk_in or negedge rst)begin // low
if(rst == 1'b0)begin
count1 <= 3'd0;
end
else begin
if(count1 >= 3'd3)begin
count1 <= 3'd0;
flag <= 1'b0;
end
else begin
if(flag == 1'b1)
count1 <= count1 + 1;
end
end
end
always@(negedge clk_in or negedge rst)begin // high
if(rst == 1'b0)begin
count2 <= 3'd0;
flag <= 1'b0;
end
else begin
if(count2 >= 3'd3)begin
count2 <= 3'd0;
flag <= 1'b1;
end
else begin
if(flag == 1'b0)
count2 <= count2 + 1;
end
end
end
endmodule