题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg y_r;
reg [1:0] s, ns;
parameter P_S0 = 2'b00 , P_S1 = 2'b01 , P_S2 = 2'b11, P_S3 = 2'b10;

//first always state change
always@(posedge clk or negedge rst_n) begin
    if(!rst_n)
        s <= P_S0;
    else
        s <= ns;
end

//secend always state shif rules combination
always@(s or C) begin
    case(s)
        P_S0: begin
            if(C)
                ns = P_S1;
            else
                ns = P_S0;
        end
        P_S1: begin
            if(C)
                ns = P_S1;
            else
                ns = P_S2;
        end 
        P_S2:begin
            if(C)
                ns = P_S3;
            else
                ns = P_S2;
        end 
        P_S3:begin
            if(C)
                ns = P_S3;
            else
                ns = P_S0;
        end 
        default: ns = P_S0;
    endcase
end

//third always output logic
//always@(posedge clk or negedge rst_n) begin
always@(*) begin
        case (s)
            P_S0: y_r = 1'b0;
            P_S1: y_r = 1'b0;
            P_S2: y_r = 1'b1;
            P_S3:begin
                 if(C) y_r = 1'b1;
                 else y_r = 1'b0;
            end
            default: y_r = 1'b0;
        endcase
end
assign Y = y_r;
endmodule