题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//
reg [1:0] cnt;
reg [3:0] data;
reg valid_r;
reg dout_r;

always @( posedge clk or negedge rst) begin
  if(!rst) begin
	cnt <= 'b0;
	valid_r <= 'b0;
	data <= 'd0;
  end
  else if (cnt == 'd3) begin
	cnt <= 'd0;
    valid_r <= 'b1;
	data <= d;
  end
  else begin
    cnt <= cnt + 'b1;
	valid_r <= 'b0;
	data <= data;
  end
end

always @ (*) begin
  case (cnt) 
    'd0: dout_r = data[3];
	'd1: dout_r = data[2];
	'd2: dout_r = data[1];
	'd3: dout_r = data[0];
  endcase
end
assign valid_in = valid_r;
assign dout = dout_r;
//*************code***********//
endmodule