题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	parameter s0=4'd0;
	parameter s1=4'd1, n_s1=4'd9;
	parameter s2=4'd2, n_s2=4'd10;
	parameter s3=4'd3, n_s3=4'd11;
	parameter s4=4'd4, n_s4=4'd12;
	parameter s5=4'd5, n_s5=4'd13;
	parameter s6=4'd6, n_s6=4'd14;
	

reg [3:0] current_state,next_state;
reg[2:0] cnt;
    always@(*)
	begin
    case(current_state)
		n_s1:next_state=n_s2;
		n_s2:next_state=n_s3;
		n_s3:next_state=n_s4;
		n_s4:next_state=n_s5;
		n_s5:next_state=n_s6;
		n_s6:next_state= data ? n_s1:s1;

			s0:next_state= data ? n_s1:s1;
			s1:next_state= data ? s2:n_s2;
			s2:next_state= data ? s3:n_s3;
			s3:next_state= data ? s4:n_s4;
			s4:next_state= data ? n_s5:s5;
			s5:next_state= data ? n_s6:s6;
			s6:next_state= data ? n_s1:s1;
	default:next_state=s0;
	endcase 
	end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
current_state<=s0;
end
else
begin
current_state<=next_state;
end
end


			always@(*)
			begin
			if(!rst_n)
			begin
			match=1'b0;
			not_match=1'b0;
			end
			else
			begin
			match = (current_state==s6);
            not_match =  (current_state==n_s6);

			end
			end

endmodule